This invention relates generally to digital integrated circuits for use in data processing computing systems and the like and more particularly, it relates to a pulse generator which is responsive only to the positive edge of an asynchronous pulse of a varying width for generating an output pulse that is synchronized to an internal clock pulse.
As is generally well known, in the field of electronic digital computing systems there is typically required the use of a microprocessor which contains numerous logic circuitry including latches, flip-flops and other storage devices. Further, the microprocessor is usually built around internally-generated signals or clock pulses which are utilized to control the timing of when certain process operations are to be performed and when data information are to be transferred. The nature of clock pulses used within the microprocessor is critical to its performance. Thus, these clocked signals are delivered to all parts of the system so that each step in the process will operate internally in a synchronous manner in relationship to the internal clock pulses.
However, many times the microprocessor will be required to interface with other integrated circuits which generates asynchronous pulse signals having variable pulse widths that occurs at different times and operates independently with respect to the timing of the internal clock pulses. As a result, the asynchronous pulse signals received by the logic circuitry may cause false triggering of the storage devices, i.e., the latches or flip-flop, and thus effect the storing of a wrong or incorrect logic state.
Accordingly, there has arisen a need of a pulse generator which receives asynchronous pulses of a varying width and generates an output pulse that is synchronized to an internal clock pulse so as to eliminate false triggering and thus allows reliable and accurate data information to be stored in the various storage devices. It would be expedient to form the pulse generator with a minimal number of component parts so as to not only improve the yield and increase the logic function density on the semiconductor integrated circuits, but also to reduce the power consumption for performance of the logic functions involved.